
`include "defines.v"

//----------------------------------------------------------------
//Module Name : IDEX_reg.v
//Description of module:
//
//----------------------------------------------------------------
//Designer:	Tang Pengyu
//Date: 2021/9/27/20:13  
//----------------------------------------------------------------

module	IDEX_reg(
	input	clk,
	input	idex_rst,
	input	idex_ena,
	
	input	i_id_rs1_r_ena,				//--csr_reg,regfile
	input	[4:0]	i_id_rs1_r_addr,	//--csr_reg,regfile
	input	i_id_rs2_r_ena,				//--regfile
	input	[4:0]	i_id_rs2_r_addr,	//--regfile
	input	i_id_rd_w_ena,				//--csr_reg,regfile
	input	[4:0]	i_id_rd_w_addr,		//--csr_reg,regfile
	input	i_id_csr_imm_ena,			
	input	[`REG_DATA_LEN-1:0]	i_id_csr_imm,		//--ls_pro
	input	[5:0]	i_id_inst_type,
	input	[7:0]	i_id_inst_opcode,
	input	[`REG_DATA_LEN-1:0]	i_id_op1,
	input	[`REG_DATA_LEN-1:0]	i_id_op2,			//--mem
	input	[`REG_DATA_LEN-1:0]	i_id_extend_imm,
	input	[6:0]	i_id_funct7,
//from ctrlid
	input	[1:0]	i_ctrlid_wb_sel,			//regfile
	input	i_ctrlid_ecall_en,					//wb
	input	i_ctrlid_mret_en,					//wb
//from	if	
	input	i_ifif_fetched,
//	input	i_ifif_time_intr_r,
	input	[`INST_ADDR_LEN-1:0] i_ifif_pc_out,
	input	[`INST_ADDR_LEN-1:0] i_ifif_addr,	
	
	output	reg o_id_rs1_r_ena,
	output	reg [4:0]	o_id_rs1_r_addr,
	output	reg o_id_rs2_r_ena,
	output	reg [4:0]	o_id_rs2_r_addr,
	output	reg o_id_rd_w_ena,
	output	reg [4:0]	o_id_rd_w_addr,
	output	reg o_id_csr_imm_ena,
	output	reg [`REG_DATA_LEN-1:0]	o_id_csr_imm,
	output	reg [5:0]	o_id_inst_type,
	output	reg [7:0]	o_id_inst_opcode,
	output	reg [`REG_DATA_LEN-1:0]	o_id_op1,
	output	reg [`REG_DATA_LEN-1:0]	o_id_op2,
	output	reg [`REG_DATA_LEN-1:0]	o_id_extend_imm,
	output	reg [6:0]	o_id_funct7,
	
	output	reg	[1:0]	o_ctrlid_wb_sel,
	output	reg o_ctrlid_ecall_en,
	output	reg o_ctrlid_mret_en,
	
	output	reg o_ifif_fetched,
//	output	reg o_ifif_time_intr_r,
	output	reg [`INST_ADDR_LEN-1:0] o_ifif_pc_out,
	output	reg [`INST_ADDR_LEN-1:0] o_ifif_addr
);

always @(posedge clk)	begin
	if(idex_rst)	begin
		o_id_rs1_r_ena <= 1'b0;
		o_id_rs1_r_addr <= 5'd0;
		o_id_rs2_r_ena <= 1'b0;
		o_id_rs2_r_addr <= 5'd0;
		o_id_rd_w_ena <= 1'b0;
		o_id_rd_w_addr <= 5'd0;
		o_id_csr_imm_ena <= 1'b0;
		o_id_csr_imm <= {`REG_DATA_LEN{1'b0}};
		o_id_inst_type <= 6'd0;
		o_id_inst_opcode <= 8'b000_00100;
		o_id_op1 <= {`REG_DATA_LEN{1'b0}};
		o_id_op2 <= {`REG_DATA_LEN{1'b0}};
		o_id_extend_imm <= {`REG_DATA_LEN{1'b0}};
		o_id_funct7 <= 7'd0;
		
		o_ctrlid_wb_sel <= 2'b00;
		o_ctrlid_ecall_en <= 1'b0;
		o_ctrlid_mret_en <= 1'b0;
		
		o_ifif_fetched <= 1'b0;
//		o_ifif_time_intr_r <= 1'b0;
		o_ifif_pc_out <= {`INST_ADDR_LEN{1'b0}};
		o_ifif_addr <= {`INST_ADDR_LEN{1'b0}};
	end
	else if(idex_ena)	begin
		o_id_rs1_r_ena <= i_id_rs1_r_ena;
		o_id_rs1_r_addr <= i_id_rs1_r_addr;
		o_id_rs2_r_ena <= i_id_rs2_r_ena;
		o_id_rs2_r_addr <= i_id_rs2_r_addr;
		o_id_rd_w_ena <= i_id_rd_w_ena;
		o_id_rd_w_addr <= i_id_rd_w_addr;
		o_id_csr_imm_ena <= i_id_csr_imm_ena;
		o_id_csr_imm <= i_id_csr_imm;
		o_id_inst_type <= i_id_inst_type;
		o_id_inst_opcode <= i_id_inst_opcode;
		o_id_op1 <= i_id_op1;
		o_id_op2 <= i_id_op2;
		o_id_extend_imm <= i_id_extend_imm;
		o_id_funct7 <= i_id_funct7;
		
		o_ctrlid_wb_sel <= i_ctrlid_wb_sel;
		o_ctrlid_ecall_en <= i_ctrlid_ecall_en;
		o_ctrlid_mret_en <= i_ctrlid_mret_en;
		
		o_ifif_fetched <= i_ifif_fetched;
//		o_ifif_time_intr_r <= i_ifif_time_intr_r;
		o_ifif_pc_out <= i_ifif_pc_out;
		o_ifif_addr <= i_ifif_addr;
	end
end


endmodule